Beat 01
Perception under noisy labels
Production dispositions are inconsistent, and pretending otherwise is how models end up confidently wrong on the floor.
Blog
Notes on Mura, transfer yield and ramp
Working notes from building a control loop for display manufacturing — written for process, yield and quality engineers.
- Process
- Perception
- Control
- Field notes
Latest
Recent writing
Why false calls are a process problem, not an inspection problem
Suppression without escape-rate measurement is not an improvement — it is a transfer of risk
Drift you can still fix: reading trajectories instead of alarms
The most valuable signal is the one still inside the window and heading out of it
The transfer-yield ceiling on microLED
Why fractional placement and bonding losses dominate the cost per good panel
Ramp is a knowledge problem
What actually takes quarters when a new panel product moves to volume
Designing write-back that equipment engineering will approve
Idempotency, fail-safe stops and the authorisation model behind recipe changes
The override is the dataset
Treating engineer corrections as the highest-value labels in the fab
Themes
What we keep writing about
Beat 02
Control with consequences
Writing a recipe is not a recommendation. The engineering standard is different and should be.
Beat 03
Economics of a good panel
Yield, scrap, repair cost and demand mix are one objective function, not four dashboards.
Beat 04
Trust as an interface
The autonomy gates are as much a product decision as any model architecture.
# closed loop, one panel
perceive substrate → tft → emitter stack → sub-pixel
plan deposition · anneal · transfer · test/bin
act recipe write-back (SECS-GEM)
sense mura ΔL* · sub-pixel opens · particles
optimise yield · ramp · scrap
log immutable audit entry ✓ signed
retrain engineer correction → model
Series
The closed-loop series
A long-form walkthrough of the loop, one stage per post.
Step 1 of 7 · perceive
Perceive the panel, not the tool
Substrate, TFT array, emitter stack and individual sub-pixels are modelled together, so a signal on one layer is read in the context of every layer beneath it.
Step 2 of 7 · plan
Plan the move that protects yield
The orchestrator plans deposition, anneal, transfer, test and bin actions against the current yield, demand mix and risk budget — not against a static recipe table.
Step 3 of 7 · act
Act through the interfaces the fab already trusts
Recipe and setpoint write-back travels over SECS-GEM/HSMS where the tool supports it, with REST and OPC-UA bridges elsewhere. Nothing bypasses fab governance.
Step 4 of 7 · sense
Sense what actually happened
Mura ΔL*, sub-pixel opens and shorts, particles, overlay and Vth maps come back as measurement, closing the loop on the action rather than assuming it worked.
Step 5 of 7 · optimise
Optimise yield, ramp and scrap together
Single-metric optimisation is how fabs trade one loss for another. The loop weighs yield, ramp time and scrap as one objective.
Step 6 of 7 · log
Log every decision immutably
Each action writes a signed, yield- and quality-grade audit entry: what was sensed, what was decided, who approved it and what changed.
Step 7 of 7 · retrain
Retrain on engineer corrections
Every override is a label. Corrections from process, yield and quality engineers flow back into the models that made the call.
Categories
Browse by topic
Perception
Mura, sub-pixel defects, particles and the trouble with production labels.
Control
Deposition, anneal and transfer control that survives contact with a real tool.
Simulation
What a panel-and-line twin has to get right to be worth gating on.
Integration
SECS-GEM, OPC-UA and the politics of write-back.
Economics
Cost per good panel, ramp weeks and where margin actually leaks.
Field notes
What we learn on the line that we could not have designed from a desk.
Editorial standard
We publish what we can defend
Posts state their assumptions, show their method and label targets as targets. If a number came from a design partner, it is published only with consent and with the baseline attached.
- Assumptions stated up front
- Method described so it can be challenged
- No customer data without written consent
- Corrections published, not quietly edited
# closed loop, one panel
perceive substrate → tft → emitter stack → sub-pixel
plan deposition · anneal · transfer · test/bin
act recipe write-back (SECS-GEM)
sense mura ΔL* · sub-pixel opens · particles
optimise yield · ramp · scrap
log immutable audit entry ✓ signed
retrain engineer correction → model
Context
Systems we write about
Deposition, litho and encapsulation
Vacuum depositionInkjet/TFE encapsulationPhotolithographyOverlay metrologyChamber telemetry
Anneal and TFT process
Excimer laser annealThermal annealVth metrologyLTPS/oxide array
Inspection, metrology and test
Mura/AOI systemsOptical uniformityArray testCell testAging
Transfer, repair and handling
Mass-transfer headsLaser repairPanel roboticsCassette logistics
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- Shadow-mode instrumentation on one wedge workflow
- Baseline measurement of yield, false calls and ramp time
- Paid pilot with a single agreed success metric
Voices from the line
What the fab floor tells us
“We do not lose panels because nobody is watching. We lose them because the signal that mattered was buried under a thousand nuisance calls.”
“Ramp is the whole game. If a new product takes two quarters of manual tuning, that is two quarters of margin we never get back.”
“Transfer yield is our ceiling on microLED. Every dead emitter is a repair cycle or a scrapped backplane.”
Quotes are illustrative composites drawn from discovery interviews with process-integration, yield and quality engineers. Named references are [PLACEHOLDER] pending design-partner consent.
The economics
What the loop is measured on
Emiteon is priced and evaluated on the numbers a fab already reports. These are design-partner targets for the first twelve months of deployment.
$26BDisplay-fab automation, process control, inspection, test and fab software market
~14%Annual growth in the segments Emiteon plays in
135%Net revenue retention target from land-and-expand
99.9%Uptime target for the fab edge runtime
Figures marked as targets are design-partner objectives, not audited results. Company operating status, customers and outcomes are [ASPIRATIONAL] until independently verified.
FAQ
Questions fabs ask first
Through three gates. Shadow mode observes and predicts with no write-back; advisory mode recommends recipe, transfer and binning moves that a process-integration or yield engineer approves; graduated autonomy releases low-risk deposition, anneal and transfer control once measured accuracy and twin validation clear the bar. High-impact decisions stay human-in-the-loop.
Reducing false calls is the wedge, not a side effect. The mura-and-defect agent is trained on true-versus-false-call labels from your own inspection history, so it separates genuine large-area non-uniformity, sub-pixel opens and shorts, particles and stains from nuisance signals, and every call is traceable to the evidence behind it.
Per-tenant isolation with recipes, panel designs and defect images scoped to your tenant, encryption in transit and at rest, SSO/RBAC, an immutable yield/quality-grade audit log and an on-prem or air-gapped option. Fleet learning shares model improvements, never your recipes.
Deposition, photolithography, encapsulation and anneal tools, Mura/AOI inspection and metrology, array and cell test, mass-transfer and repair stations, robotic handling and MES — vendor-neutral via SECS-GEM/HSMS where the tool supports it, with REST and OPC-UA bridges elsewhere.
Every pixel, perfectly uniform.
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